I'm Ario Kian

Hardware Security Researcher

Reconfigurable System Researcher.

FPGA Developer.

Embedded System Designer.

Welcome

Tehran, Iran.

Resume & CV

About Me

Know Me More

I'm Ario Kian, FPGA based Embedded System Researcher and Side-Channel Analyzer

Experienced FPGA Developer with great skills in modeling and implementing DSP and Secure applications in VHDL with a considerable background in developing Systems with the ability of Dynamic Partial Reconfigurations using Xilinx Zynq MPSoC Devices.

Graduated from Shahid Beheshti University, Faculty of Computer Science and Engineering in Master's Degree, member of the Integrated Circuits Automated Design Lab, with research background in designing secure dynamically reconfigurable systems against Side-Channel Analysis Attacks with 1 published paper in CADs 2020 Conference.

In general, i'm a curious person about anything related to modeling, designing and implementing systems based on FPGA and Zynq Devices and also eager to research in fields of Reconfigurable Systems, Side-Channel Analysis and Digital Signal Processing.

I also have background and work experience in other specific domains such as:

  • Embedded System Design using Arduino and STM32 based platforms
  • PCB Design using Altium Designer tool up to 4 layers
  • Web application development using Angular and NodeJS and Sqlite3

Download CV

6+

Years Experiance

1

Published Papers

20+

Projects Prticipated

10+

Professional Courses Participated

Fields of Interest

What I'm willing to Do?

Reconfigurable Computing

Hardware/Software Codesign

Real-Time Operating Systems

Digital Signal Processing

Hardware Security
(Side-Channel Analysis Attacks)

Summary

Resume

Education

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2016 - 2019

Master of Science (MSc) Degree

Shahid Beheshti University, Tehran, Iran

Computer Engineering (Computer Systems Architecture)

  • GPA(Total): 3.4/4

  • Research Area:
    “Hardware Security Analysis of Reconfigurable Systems”

  • Thesis:
    “Security Improvement of FPGA-based Design Against Side-Channel Analysis Attacks using Dynamic Partial Reconfiguration”

2011 - 2015

Bachelor of Science (BSc) Degree

Guilan University

Computer Engineering (Hardware Engineering)

  • GPA(Last two years): 3.1/4



TA Experiance

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Spring 2019

Embedded System Design Modeling and Methodology

Master Degree Course
Shahid Beheshti University
Lecturer: Dr.Seyed-Hosein Attarzadeh-Niaki

Spring 2018

Computer Architecture Lab

Bachelor Degree Course
Shahid Beheshti University
Lecturer: Dr.Zohre Beiki

Fall 2017

Computer Architecture Lab

Bachelor Degree Course
Shahid Beheshti University
Lecturer: Dr.Zohre Beiki

Spring 2017

Digital Circuit, Logic and Design

Bachelor Degree Course
Shahid Beheshti University
Lecturer: Dr.Ali Jahanian

Fall 2016

Digital Circuit, Logic and Design

Bachelor Degree Course
Shahid Beheshti University
Lecturer: Dr.Ali Jahanian

Online Courses

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Udemy

Digital Signal Processing (DSP) From Ground Up™ with MATLAB

Practical DSP with Matlab : FFT, Filter Design, Convolution, IIR, FIR, Hamming Window, Linear Systems, ECG processing

Lecturer: Israel Gbati
Link: https://www.udemy.com/course/matlab_dsp/
course progress:65%

Coursera

FPGA computing systems: Partial Dynamic Reconfiguration

University: Politecnico Di Milano

Lecturer: Marco Domenico Santambrogio
Link: https://www.coursera.org/learn/copy-of-fpga-intro?
course progress:60%

Publicaitons

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19-20 Aug 2020

20th International Symposium on Computer Architecture and Digital Systems (CADS)

Protecting the FPGA IPs against Higher-order Side Channel Attacks using Dynamic Partial Reconfiguration

Authors:
Ario Kian, Hamed Hosseintalaee, Ali Jahanian

Link: https://ieeexplore.ieee.org/abstract/document/9211862

Sep 2022

In Preparation

Analytical Review on the Side-Channel Security Aspects of Partial Reconfigurable Systems

Authors:
Ali Jahanian, Milad Salimian, Ario Kian



Work Experience

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Oct 2020 - Present

Embedded Developer/Altium PCB Designer

SEA (Speed Energy Aryanic) . Part-time

Current Projects:

  • Development of a minimal Web Server using NodeJS providing a Web Interface to Capture, Log and Monitor Information Received from Embedded Devices through Serial Port
Previous Projects:
  • PCB Design for Battery State Monitoring Devices.
  • Development of a Control Unit for a Step Based Stabilizer.
  • Development of a Control Unit for an Automatic Transfer Switch(ATS).

Mar 2020 - Sep 2020

FPGA Interface Developer

Mana Pardaz Control · Full-time

Projects:

  • Implemention of UART Serial Interface in HDL for Xilinx Artix-7 FPGA.
  • Extraction of Xilinx FPGAs DNA Code and Use it for preventing the cloned design to be executed on another Device.
  • Area based Optimizion of HDL Projects using Specific Embedded Resources in Xilinx FPGAs such as BRAMs, DSP blocks, ...
  • Sampling of data passing through Data and Control Bus from a custom processing platform using Chipscope environment

May 2017 - Mar 2020

Emedded System Developer and Researcer

Nano Afzar Tarashe . Part-time

Projects:

  • ِResearch on SNMP based Monitoring and Controling Devices Specific for Uninterruptible Power Supllies(UPS).
  • ِTest and Analyze the Claimed Specifications and Parameters of UPS devices from Different Vendors



Honors & Awards

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  • Dec 5th-6th 2018

    5th National Digital System Design Contest of Iran

    Branch:
    ASIC Design

    Ranking: Third Place

    Contest Topic:
    Design and implementation of a Direct Digital Synthesizer (DDS)

My Skills

  • Programming and HDL Languages

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    VHDL\Verilog

    C/C++

    Matlab

    Python

    Javascript

    Angular

    NodeJS

    SQL

  • Processing Devices and Platforms

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    Field-Programmable Gate Arrays (FPGA)

    Zynq APSoCs

    Rasperry Pi

    Arduino

    STM32 Microcontrollers

  • IDEs and Tools

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    Xilinx Vivado Design Suite

    Xilinx ISE Design Suite

    Matlab

    Simulink

    Altium Designer

    Eclipse IDE

    Keil UVision 5

    Visual Studio Code

Download CV

Portfolio

My Work

Battery State Monitoring
PCB Design
Light-Weight Web Server
Web Development
5th National Digital System Design Contest of Iran
ASIC Design
Shahid Beheshti University BehComp Seminar
Embedded System Department
SEA Company
Hardware Security and DNA Computing Lab
Shahid Beheshti University

References

References

Ali Jahanian Assistant Professor
Faculty of Computer Science and Engineering, Shahid Beheshti University

Email:
jahanian@sbu.ac.ir
Home Page:
http://facultymembers.sbu.ac.ir/jahanian/
Scholar Page:
https://scholar.google.com/citations?user=gTht4nwAAAAJ&hl=en

Zohre Beiki Assistant Professor
Faculty of Computer Engineering, University of Isfahan (UI)

Email:
z.beiki@eng.ui.ac.ir
Home Page:
https://engold.ui.ac.ir/~z.beiki/
Scholar Page:
https://scholar.google.com/citations?user=kYgnTKoAAAAJ&hl=en

Contact

Get in Touch

Address

4th Floor, Plot No.8,
16'th Avenue, Yousefabad Avenue.
Tehran, Iran

(+98) 919 8035391

akianazad@gmail.com
a.kianazad@mail.sbu.ac.ir

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